Tech Stack: IFM CR1081 Master PLC, IFM CR0403 Distributed I/O Slaves, PQ Controls M115 CANopen Joysticks, CoDeSys V2.3 (IEC 61131-3 FBD & ST), CANopen (CiA 301) & SAE J1939.
The Scope: Reverse-engineered legacy PLC code across three controller types and executed a $20,000 directional control retrofit across two $400,000 tracked mobile drill rigs to eliminate $400/hour downtime events caused by Data Link Layer MAC ID collisions and eradicate a critical life-safety hydraulic track runaway hazard.
The Engineering Challenge:
Deterministic Latency & Protocol Tuning: Collaborated with PQ Controls firmware engineers to specify a custom drop-in 3-byte Little-Endian UINT16 payload (100 Forward / 1028 Neutral / 1950 Reverse) without J1939 bit-packing. Reconfigured Object Dictionary EDS files from acyclic-synchronous to cyclic-synchronous (TxPDO1 with 1 SYNC) and reduced the CANopen Manager SYNC cycle period from 100ms (100,000 µs) to 10ms (10,000 µs), ensuring the master PLC registers neutral return within 10 milliseconds to prevent missed-packet track runaways.
Fail-Safe Hardware Fault Mitigation: Diagnosed physical-layer node-ID resistor faults that caused Data Link Layer MAC ID collisions (Node 76 defaulting to Node 74) and CAN Bus-Off states, where the legacy NORM_DINT scaling block interpreted a 0 input buffer as a maximum reverse command (100). Implemented FBD out-of-bounds window comparators (LE 90 and GE 1960) routed into a SEL multiplexer block to dynamically isolate the scaling math and force 0 PWM output to the hydraulic drive pumps during wire shorts or Bus-Off faults.
Asynchronous Boot & Programmatic NMT Auto-Healing: Resolved boot sequence desynchronization across isolated front/rear fuse panel power domains where rear joysticks booted after the master’s initial NMT broadcast and remained stranded in the Pre-Operational state holding a 0x00 boot-up frame. Architected a closed-loop network healer using CAN_RX buffer snooping and isolated 3-second stabilization timers (Network_Heal_Node74 and Network_Heal_Node75) to dynamically broadcast a global NMT Start command (16#01, 16#00) via CAN_TX.
Click to expand.
Tech Stack: IFM CR1081 Master PLC (Dual-Channel CAN), Caterpillar C6.6L Engine ECU, IFM CR0403 CANopen Slaves, SAE J1939 (250 kbps), CANopen (CiA 301), CoDeSys V2.3 (ST & FBD).
The Scope: Designed autonomous compressor and hydraulic cooling firmware for a 12V Jackson Seismic Drill Rig, protecting a $10,200 GHH RAND rotary screw compressor from thermal meltdowns while eliminating 1-to-2-hour ($400–$800) downtime events and fluid leaks.
The Engineering Challenge:
Stiction Breakaway & Hydraulic Kinetic Shock Mitigation: Field testing revealed a physical valve stiction breakaway threshold of 275 PWM (out of 475 PWM maximum saturation), where standard 0–475 PWM ramping caused dead-spool delay followed by violent kinetic shock. Designed a Base-and-Delta split-ramp algorithm in Structured Text that strips the inactive 0–274 PWM deadband, jumps instantaneously to the 275 PWM baseline upon cooling demand, and passes the active flow delta (275–475 PWM) through a RAMP_REAL block restricted to 40 PWM/sec for a smooth 5.0-second spool-up.
Scan-Cycle Race Condition & Bootloader Diagnostics: Utilized the CoDeSys Output Cross-Reference tool and an IFM EC2112 CANfox analyzer to diagnose a mid-scan double-write race condition where ~100 Hz asynchronous PDO updates from the CR2033 slave executed through top-level NORM_REAL FBD blocks and overwrote manual F7 ST test forces. Isolated the math blocks for live validation by forcing raw incoming analog signals (HYD_TEMP) at the root, and resolved SDO firmware flashing aborts (Communication Error #0) caused by CANbus saturation by configuring Target ID 127, enabling Motorola (Big-Endian) byte ordering for the Freescale processor, and using an HMI hardware bootloader trap.
Fail-Safe Compressor & Sensor Fault Overrides: Programmed hardcoded ST hysteresis deadbands to prevent contactor chatter and proportional surging on the Mavis Air/Oil Separator tank (MAWP 250 PSI @ 250°F). Integrated X_OUT_OF_RANGE boolean flags from the FBD NORM_REAL blocks so any open circuit, short circuit, or CR2033 node failure triggers COMP_TEMP_FAULT OR HYD_TEMP_FAULT, bypassing calculated math to force a mandatory 100% cooling state (475 PWM).
Tech Stack: IFM CR1081 Master PLC (Dual-Channel CAN), Caterpillar C6.6L Engine ECU, IFM CR0403 CANopen Slaves, SAE J1939 (250 kbps), CANopen (CiA 301), CoDeSys V2.3 (ST & FBD).
The Scope: Remediated a critical arctic (-30°C) glow plug preheat indicator failure and resolved corrupted multi-sensor engine telemetry across a dual-bus CANopen and SAE J1939 architecture on heavy-duty mobile drilling equipment.
The Engineering Challenge:
J1939 Array Pointer Alignment: Traced a premature dropout of the cabin “Wait to Start” indicator (gWaitToStartLamp), which illuminated for only a second at -30°C instead of executing the 15–30 second preheat duration, to an off-by-one pointer shift on the J1939_RX listener block for PGN 65252 (0xFEE4). Standardized Pgn65252_Data from a 1-indexed array (ARRAY[1..8] OF BYTE) to a 0-indexed array (ARRAY[0..7] OF BYTE) so the Structured Text bitmask Pgn65252_Data[4].0 AND NOT(Pgn65252_Data[4].1) accurately evaluated Byte 5 (SPN 1081).
Distributed CANopen I/O Cross-Mapping: Discovered via schematic tracing on CR0403 Slave 1 that physical input %IB8 (wired to the Cat ECU’s TAN PREHEAT WAIT conductor, mapped to PREHEAT_WAIT) and %IB9 (wired to the GREY WARMING LAMP fault conductor, mapped to ENGINE_WARNING_LAMP) were cross-mapped in the master logic. Refactored the boolean expression to OR the J1939 bitmask with PREHEAT_WAIT rather than the ECU’s brief key-on warning lamp bulb-check pulse.
Cross-Platform ECU Telemetry Filtering: Diagnosed static, out-of-range HMI readings for Fuel Temperature (215) and Oil Temperature (1767) on PGN 65262 (0xFEEE) caused by a cloned legacy Cummins function block (EngineCummins_2) scaling standard J1939 16#FF / 16#FFFF “Not Available” padding bytes from the Caterpillar C6.6 ECU. Implemented bitwise validation masking on the status register ((wSignalsAvail AND 16#0001) <> 0) to confirm active SPNs prior to HMI scaling and established standalone J1939_RX listener blocks for Cat-specific PGNs.
Tech Stack: IFM CR1081 Mobile Display Controller, CoDeSys V2.3 Target Visualization, IEC 61131-3 Structured Text (Display_Visual_Flags POU) & Function Block Diagram, SAE J1939 & CANopen.
The Scope: Overhauled the primary operator HMI dashboard (P00030) and audited critical hydraulic safety shutdown interlocks on a JES-800 Track Drill Rig, slashing screen transition latency by 75% (from 10–12 seconds down to 2–3 seconds) and reducing dynamic object initialization overhead by 66%.
The Engineering Challenge:
Centralized PLC Visualization Driver: Eliminated compiler watch-expression warnings and HMI polling bottlenecks by designing a dedicated Structured Text POU to execute all threshold comparisons, scaling math, and J1939 conversions inside the fast 10–30 ms PLC scan cycle.
Vector Graphics & Single-Object Color Injection: Replaced seven CPU-intensive circular vector gauges, which required heavy trigonometric pixel plotting on page initialization, with C-formatted (%.0f, %1.1f) high-contrast digital readouts and linear track pressure bar graphs, while disabling background XML Web-Visualization compilation. Transitioned from 3-layer stacked invisibility boxes (Hide booleans) to single rectangle objects dynamically colored via 32-bit hexadecimal DWORD variables (16#00BBGGRR), reducing dynamic object initialization overhead by 66%.
Safety Interlock Chain Auditing: Audited global variable tables (Global_Variables) and control routines (TRACK_DRILL_CONTROL in ST and PRESS_VAR in FBD) prior to binding HMI indicators, verifying the hydraulic oil level safety interlock where an inverted switch (HYDRAULIC_LEVEL) sets the fault flag (HYDRAULIC_OIL_LEVEL), triggers a 3-second delay timer (LOW_HYD_OIL_DELAY), and executes an emergency engine shutdown (ECU_POWER := FALSE).
Before and After Graphics Optimization
Tech Stack: Emerson DeltaV DCS, CHARM I/O Architecture, IEC 61131-3 Function Block Diagrams, HART Instrumentation, ISA-5.1 P&IDs.
The Scope: Co-Led a multidisciplinary team of six (Instrumentation, Electrical, and Mechanical Technologists) to fully commission a $200,000 capital investment heat exchanger plant, automating control to maintain a product outlet temperature between 20°C and 50°C.
The Control Strategy: Designed a static model predictive feedforward control strategy featuring feedback trim and an inner cascaded steam flow loop to mitigate upstream process disturbances.
Click diagrams to expand P&ID, Control Blocks, and DeltaV logic.
Tech Stack: Raspberry Pi 4, Python, Ultramic 384k EVO, Pimoroni Enviro+ HAT, and LTR-559 light sensor, BME280 (temperature, pressure, humidity), MPU-6050 6DOF Accelerometer, PyAudio, I2C, GPIO Interfacing.
The Scope: Co-developed a low-cost, standalone Environmental Sensor Module (ESM) for biomedical laboratory vivariums to capture high-fidelity ultrasonic rodent vocalizations alongside synchronized environmental data (temperature, pressure, humidity, light intensity, and gas concentrations).
The Engineering Challenge:
Data & Memory Management: Engineered a custom Python application utilizing PyAudio to handle massive ultrasonic data streams, resolving hardware limitations by optimizing RAM allocation on the Raspberry Pi to support extended, unattended continuous recording modes.
Hardware Interrupts: Designed a triggered recording architecture utilizing 5V GPIO pins, implementing programmable lead and lag time data buffers to precisely capture acoustic windows immediately before and after mechanical vivarium events.
Sensor Calibration: Diagnosed and mitigated thermal interference by physically isolating the Enviro+ temperature sensor from the Raspberry Pi’s CPU heat generation, ensuring highly accurate ambient laboratory readings
Click diagrams to expand System Architecture, Project Poster, Block Diagram.
Tech Stack: C/C++, POSIX, Linux/Unix CLI, Multithreading (pthreads), IPC (Pipes), Mutexes/Semaphores, Process Management.
The Scope: Engineered a custom command-line interface (CLI) shell to manage process execution, alongside a concurrent job simulator to handle thread resource allocation and prevent deadlocks in a strict POSIX environment.
The Engineering Challenge:
Process Management & IPC: Designed safe process generation using fork() and execlp(), bypassing standard high-level system() calls. Engineered custom inter-process communication (IPC) pipes between parent and child processes to instantly detect execution failures and prevent defunct “zombie” tasks from populating the accepted task registry.
Concurrency & Deadlock Prevention: Developed safe multithreading architectures using pthreads to handle parallel task execution. Implemented strict resource allocation protocols utilizing pthread_mutex_t locks and semaphores (sem_trywait, sem_post) to prevent race conditions and ensure thread safety during shared resource allocation (successfully stress-tested against the Dining Philosophers scenario).
Tech Stack: VHDL, FPGA (Zybo Z7), Xilinx Vivado, Register Transfer Level (RTL) Design, Finite State Machines (FSM), Combinational/Sequential Logic.
The Scope: Designed, synthesized, and verified complex digital systems on an FPGA, culminating in the development of a fully functional 8-bit CPU featuring a dedicated datapath and FSM controller.
The Engineering Challenge:
CPU Architecture: Engineered a complete 8-bit processor utilizing accumulators, registers, multiplexers, and an ALU. Designed the control logic to execute custom instruction sets (Fetch-Decode-Execute), incorporating positive/zero flags and absolute jump (JMPZ) memory addressing.
Sequential State Machines: Developed complex Mealy Finite State Machines (FSM) for bit-serial sequence detection and automated hardware logic. Resolved hardware timing constraints by implementing custom clock dividers (62.5M division factor) to achieve 1 Hz execution on the physical board.
Combinational Logic Optimization: Synthesized 3:2 and 7:3 priority encoders by deriving Boolean functions from truth tables and K-maps, utilizing “glue logic” to modularly combine smaller sub-systems into complex logic matrices.
Tech Stack: ARM Cortex-M4 (Nucleo-L432kc), Thumb-2 Assembly, Memory Management (Stack/Heap), Hardware Interfacing (GPIO), Bitwise Operations.
The Scope: Developed a comprehensive suite of bare-metal assembly routines for an ARM processor, advancing from low-level memory manipulation and arithmetic to full physical hardware interfacing with external PCB peripherals.
The Execution & Engineering Challenge:
Memory Management & Pointers: Mastered multiple addressing modes (Register Indirect with Offset, Indexed, and mimicked Postincrement) to manipulate data arrays directly in memory. Adhered strictly to AAPCS calling conventions by managing stack frames with PUSH and POP to preserve Link Registers (lr) and subroutine states during a recursive Bubble Sort implementation.
Deterministic Optimization: Replaced costly arithmetic cycles with high-speed bitwise operations, utilizing Logical Shift Left (LSL) and Logical Shift Right (LSR) to execute binary multiplication and division for a Trapezoidal Rule integral calculator.
Hardware Interfacing & GPIO: Engineered an assembly driver to interface the microcontroller with a custom 8×8 LED matrix PCB, controlling 74LS138 decoders and 74HC04 inverters via direct GPIO pin manipulation (PA8-PA11, PB0, PB1) based on serialized keystroke inputs.
Role: Production Intern, Benchmark International
Core Competencies: 5S Standardization, Kanban Workflows, KPI Measurement, Cycle & Takt Times, Workflow Auditing
The Scope: Applied lean manufacturing principles and deployed 5S standardization across manufacturing stations to minimize assembly errors and improve operational repeatability.
The Execution: Physically reorganized assembly floor footprints, deployed custom shadow boards, and transformed highly cluttered, disorganized workspaces into standardized, high-visibility operational zones.
The Impact: Audited physical workflows, formulated production reports, and recommended comprehensive KPI measurement frameworks to establish baseline cycle times, takt times, and throughput capacity across the assembly lines. This initiative drastically reduced tool-retrieval time, mitigated physical safety hazards, and fostered a culture of continuous improvement on the floor.
